Package iverilog-0.9.5-1

Icarus Verilog is a Verilog compiler that generates a variety of engineering formats, including XNF and EDIF netlists for synthesis, and waveform files from simulation. It strives to be true to the IEEE-1364 standard. A testbench is available at http://sourceforge.net/projects/ivtest This package provides the latest stable release. If you need synthesis, you may want to stick with the 0.8.x series in the 'iverilog08' package. You may have both this package and iverilog08 installed at the same time.