Package iverilog-snapshot-20111127-1

Icarus Verilog is a Verilog compiler that generates a variety of engineering formats, including XNF and EDIF netlists for synthesis, and waveform files from simulation. It strives to be true to the IEEE-1364 standard. A testbench is available at http://sourceforge.net/projects/ivtest This package is a development snapshot. If you would like the latest tested release, please use the iverilog package.