Package iverilog08-0.8.7-1000

Icarus Verilog is a Verilog compiler that generates a variety of engineering formats, including XNF and EDIF netlists for synthesis, and waveform files from simulation. It strives to be true to the IEEE-1364 standard. A testbench is available at http://sourceforge.net/projects/ivtest This package provides the latest in the legacy 0.8.x tree. See the 'iverilog' or 'iverilog-snapshot' packages for the latest version, or use this package if synthesis is not working in the later releases. You may have both this package and iverilog08 installed at the same time. This package installs the tools with a '-0.8' suffix; e.g. 'iverilog-0.8'.